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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
MC-45D16CD641KS
16 M-WORD BY 64-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)
Description
The MC-45D16CD641KS is a 16,777,216 words by 64 bits DDR synchronous dynamic RAM module on which 8 pieces of 128M DDR SDRAM: PD45D128164 are assembled. These modules provide high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction.
Features
* 16,777,216 words by 64 bits organization * Clock frequency
Part number /CAS latency Clock frequency (MAX.) MC-45D16CD641KS-C75 CL = 2.5 CL = 2 MC-45D16CD641KS-C80 CL = 2.5 CL = 2 133 MHz 100 MHz 125 MHz 100 MHz DDR SDRAM SO DIMM Design specification Rev.1.0 compliant Module type
* Fully Synchronous Dynamic RAM with all signals except DM, DQS and DQ referenced to a positive clock edge * Double Data Rate interface Differential CLK (/CLK) input Data inputs and DM are synchronized with both edges of DQS Data outputs and DQS are synchronized with a cross point of CLK and /CLK * Quad internal banks operation * Possible to assert random column address in every clock cycle * Programmable Mode register set /CAS latency (2, 2.5) Burst length (2, 4, 8) Wrap sequence (Sequential / Interleave) * Automatic precharge and controlled precharge * CBR (Auto) refresh and self refresh * 2.5 V 0.2 V Power supply for VDD * 2.5 V 0.2 V Power supply for VDDQ * SSTL_2 compatible with all signals * 4,096 refresh cycles / 64 ms * Burst termination by Precharge command and Burst stop command * 200-pin dual in-line memory module (Pin pitch = 0.6 mm) * Unbuffered type * Serial PD
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information.
Document No. E0187N10 (Ver. 1.0) Date Published August 2001 (K) Printed in Japan
C
Elpida Memory, Inc. 2001
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
Ordering Information
Part number Clock frequency (MAX.) 133 MHz Package Mounted devices
MC-45D16CD641KS-C75
200-pin Dual In-line Memory Module 8 pieces of PD45D128164G5 (Rev. K) (Socket Type) (10.16 mm (400) TSOP (II))
MC-45D16CD641KS-C80
125 MHz
Edge connector: Gold plated 31.75 mm height
2
Preliminary Data Sheet E0187N10
Pin Configuration
200-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated) /xxx indicates active low signal.
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD NC NC VSS NC NC VDD NC NC VSS VSS VDD VDD CKE0 NC A11 A8 VSS A6 A4 A2 A0 VDD BA1 /RAS /CAS /S1 NC VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD /CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 NC VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD NC NC VSS NC NC VDD NC NC VSS CK2 /CK2 VDD CKE1 NC NC A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 /WE /S0 NC VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD VDDID 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
A0 - A11 BA0, BA1 DQ0 - DQ63 CK0 - CK2 /CK0 - /CK2 CKE0 /S0, /S1 /RAS /CAS /WE DQS0 - DQS7
: Address Inputs : SDRAM Bank Select : Data Inputs/Outputs : Clock Input : Clock Input : Clock Enable Input : Chip Select Input : Row Address Strobe : Column Address Strobe : Write Enable : Low Data Strobe High Data Strobe
[Row: A0 - A11, Column: A0 - A9]
(positive line of differential pair) (negative line of differential pair)
DM(0 - 7) / DQS(9 - 16) : Low Data Masks / SA0 - SA2 SDA SCL VDD VSS VDDID VDDQ VREF VDDSPD NC /RESET : Address Input for EEPROM : Serial Data I/O for PD : Clock Input for PD : Power Supply : Ground : VDD Identification Flag : Power Supply for DQ and DQS : Input Reference : Power supply for EEPROM : No Connection : Reset Input
Preliminary Data Sheet E0187N10
3
Block Diagram
/S1 /S0 RS DQS0 RS DM0 8 DQ0 to DQ7 RS DQS1 RS DM1 8 DQ8 to DQ15 RS I/O8 to I/O15 I/O8 to I/O15 DQ40 to DQ47 RS I/O0 to I/O7 UDQS UDM I/O0 to I/O7 UDQS UDM DQ32 to DQ39 RS DQS5 RS DM5 8 RS I/O8 to I/O15 RS DQS6 RS LDM 8 DQ16 to DQ23 RS DQS3 RS DM3 8 DQ24 to DQ31 RS I/O8 to I/O15 I/O8 to I/O15 DQ56 to DQ63 RS I/O0 to I/O7 UDQS UDM I/O0 to I/O7 UDQS UDM DQ48 to DQ55 RS DQS7 RS DM7 8 RS I/O8 to I/O15 I/O8 to I/O15 UDM UDM UDQS LDM DM6 8 RS I/O0 to I/O7 I/O0 to I/O7 UDQS LDM LDM LDQS I/O8 to I/O15 UDM UDM UDQS LDM LDM DM4 8 RS I/O0 to I/O7 I/O0 to I/O7 UDQS LDQS RS DQS4 RS LDM LDM LDQS
/S
LDQS
/S
/S
LDQS
/S
D0
D4
D2
D6
RS DQS2 RS DM2 LDQS
/S
LDQS
/S
/S
LDQS
/S
D1
D5
D3
D7
BA0 to BA1 A0 to AN /RAS /CAS /WE CKE0 CKE1 VDDSPD VREF VDD
Serial PD SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D3) SDRAMs (D4 to D7) SPD SDRAMs (D0 to D7) SDRAMs (D0 to D7), VDD and VDDQ CK0 /CK0 CK1 /CK1 CK2 /CK2 4 loads 4 loads 0 loads SCL SA0 SA1 SA2 SCL A0 A1 A2 SDA SDA
WP
VSS VDDID Open
SDRAMs (D0 to D7), SPD Notes : 1. DQ wiring may differ from that described in this drawing; however DQ/DM/DQS relationships are maintained as shown. VDDID strap connections: (for memory device VDD, VDDQ) Strap out (open): VDD = VDDQ Strap in (closed): VDD VDDQ
Remarks 1. The value of all resistors of DQs, DQSs, DM/DQSs is 22 . 5% 2. D0 - D7: PD45D128164 (2M words x 16 bits x 4 banks)
4
Preliminary Data Sheet E0187N10
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 1 ms and then, execute Power on sequence and CBR (Auto) refresh before proper device operation is achieved.
Absolute Maximum Ratings
Parameter Voltage on power supply pin relative to VSS Voltage on input pin relative to VSS Short circuit output current Power dissipation Storage temperature Symbol VDD, VDDQ VT IO PD Tstg Condition Rating -0.5 to +3.6 -0.5 to +3.6 50 12 -55 to +125 Unit V V mA W C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Supply voltage Supply voltage for DQ, DQS Input reference voltage Termination voltage High level dc input voltage Low level dc input voltage Input differential voltage (CLK and /CLK) Input crossing point voltage (CLK and /CLK) Operating ambient temperature Symbol VDD VDDQ VREF VTT VIH (DC) VIL (DC) VID (DC) VIX TA Condition MIN. 2.3 2.3 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 0.36 0.5 x VDDQ-0.2 0 VREF TYP. 2.5 2.5 MAX. 2.7 2.7 0.51 x VDDQ VREF + 0.04 VDD + 0.3 VREF - 0.15 VDDQ + 0.6 0.5 x VDDQ+0.2 70 Unit V V V V V V V V C
Capacitance (TA = 25 C, f = 100 MHz)
Parameter Input capacitance Symbol CI1 CI2 CI3 CI4 Data input/output capacitance CI/O1 Test condition A0 - A11, BA0, BA1, /RAS, /CAS, /WE CK0 - CK2, /CK0 - /CK2 CKE0 /S0, /S1 DM(0-7) / DQS(9-16), DQS0 - DQS7 CI/O2 DQ0 - DQ63 TBD TBD MIN. TBD TBD TBD TBD TBD TYP. MAX. TBD TBD TBD TBD TBD pF Unit pF
Preliminary Data Sheet E0187N10
5
DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Test condition /CAS Grade latency -C75 MIN. MAX. Unit Notes
Operating current (ACT-PRE)
IDD0
tRC = tRC(MIN.), tCK = tCK (MIN.), One bank, Active-precharge, DQ, DM and DQS inputs changing twice per clock cycle, Address and control inputs changing once per clock cycle tRC = tRC(MIN.), tCK = tCK (MIN.), One CL = 2 bank, Active-read-precharge, IO = 0 mA, Burst length = 2, CL = 2.5 Address and control inputs changing once per clock cycle CKE VIL(MAX.), tCK = tCK(MIN.), All banks idle, Power down mode
920
mA
-C80
840
Operating current (ACT-READ-PRE)
IDD1
-C75 -C80 -C75 -C80
980 920 1020 960 80 400
mA
1
Precharge power down standby current Idle standby current
IDD2P IDD2N
mA mA
CKE VIH(MIN.), tCK = tCK(MIN.), /CS VIH(MIN.), All banks idle, Address and other control inputs changing once per clock cycle CKE VIL(MAX.), tCK = tCK(MIN.), One bank active, Power down mode /CS VIH(MIN.), CKE VIH(MIN.), tCK = tCK(MIN.), tRC = tRAS(MAX.), One bank, Active-precharge, DQ, DM and DQS inputs changing twice per clock cycle, Address and other control inputs changing once per clock cycle tCK = tCK(MIN.), Continuous burst read, Burst length = 2, IO = 0mA, One bank active, Address and control inputs changing once per clock cycle tCK = tCK(MIN.), Continuous burst write, Burst length = 2, One bank active, Address and control inputs changing once per clock cycle tRFC = tRFC(MIN.) CL = 2 -C75 -C80 CL = 2.5 -C75 -C80 CL = 2 -C75 -C80 CL = 2.5 -C75 -C80 -C75 -C80
Active power down standby current Active standby current
IDD3P IDD3N
400 560
mA mA
Operating current (Burst read)
IDD4R
1080 1080 1340 1280 1040 1040 1300 1240 1360 1280 16
mA
2
Operating current (Burst write)
IDD4W
mA
2
CBR (Auto) refresh current
IDD5
mA
Self refresh current
IDD6
CKE 0.2 V
mA
Notes 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. 2. IDD4R and IDD4W depend on output loading and cycle rates. Specified values are obtained with the output open. DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter Input leakage current Output leakage current Output high current Output low current Symbol II(L) IO(L) IOH IOL Test condition VI = 0 to 3.6 V, all other pins not under test = 0 V DOUT is disabled, VO = 0 to VDDQ + 0.3 V VOUT = VDDQ - 0.43 V VOUT = 0.35 V MIN. -5 -5 -15.2 15.2 MAX. 5 5 Unit Notes
A A
mA mA
6
Preliminary Data Sheet E0187N10
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
Parameter Input Reference voltage (Input timing measurement reference level) Termination voltage (Output timing measurement reference level) High level ac input voltage Low level ac input voltage Input differential voltage (CK0 - CK2 and /CK0 - /CK2) Input signal slew rate Symbol VREF VTT VIH(ac) VIL(ac) VID(ac) SLEW Value VDDQ x 0.5 VREF VREF + 0.31 VREF - 0.31 0.7 1 Unit V V V V V V/ns 2 1 Notes
Notes 1. Output waveform timing is measured where the output signal crosses through the VTT level. 2. Slew rate is to be maintained in the VIL (ac) to VIH(ac) range of the input signal swing. SLEW = (VIH(ac)VIL(ac))/ t
VTT RT = 50 Output CLOAD = 30 pF
Preliminary Data Sheet E0187N10
7
Synchronous Characteristics
Parameter Symbol -C75 (PC266B) MIN. Clock cycle time CL = 2.5 CL = 2 CLK high-level width CLK low-level width DQ output access time from CLK, /CLK DQS output access time from CLK, /CLK DQS-DQ skew (for DQS and associated DQ signals) DQS-DQ skew (for DQS and all DQ signals) Data out low-impedance time from CLK, /CLK Data out high-impedance time from CLK, /CLK Half clock period DQS read preamble DQS read postamble DQ-DQS hold, DQS to first DQ to go non-valid, per access DQ and DM input setup time DQ and DM input hold time DQ and DM input pulse width (for each input) DQS write preamble setup time DQS write preamble Write postamble Write command to first DQS latching transition DQS input high pulse width DQS input low pulse width DQS falling edge to CLK setup time DQS falling edge hold time from CLK Address and control input setup time Address and control input hold time Address and control input pulse width Internal write to read command delay tCH tCL tAC tDQSCK tDQSQ tDQSQA tLZ tHZ tHP tRPRE tRPST tQH tDS tDH tDIPW tWPRES tWPRE tWPST tDQSS tDQSH tDQSL tDSS tDSH tIS tIH tIPW tWTR tCK 7.5 10 0.45 0.45 -0.75 -0.75 -0.5 -0.5 -0.75 -0.75 tCH, tCL 0.9 0.4 tHP - 0.75 0.5 0.5 1.75 0 0.25 0.4 0.75 0.35 0.35 0.2 0.2 0.9 0.9 2.2 1 0.6 1.25 1.1 0.6 MAX. 15 15 0.55 0.55 0.75 0.75 0.5 0.5 0.75 0.75 -C80 (PC200) MIN. 8 10 0.45 0.45 -0.8 -0.8 -0.6 -0.6 -0.8 -0.8 tCH, tCL 0.9 0.4 tHP - 1 0.6 0.6 2 0 0.25 0.4 0.75 0.35 0.35 0.2 0.2 1.1 1.1 2.5 1 0.6 1.25 1.1 0.6 MAX. 15 15 0.55 0.55 0.8 0.8 0.6 0.6 0.8 0.8 tCK tCK ns ns ns ns ns ns ns tCK tCK ns ns ns ns ns tCK tCK tCK tCK tCK tCK tCK ns ns ns tCK ns Unit Note
Remark These specifications are applied to the monolithic device.
8
Preliminary Data Sheet E0187N10
Asynchronous Characteristics
Parameter Symbol -C75(PC266B) MIN. ACT to REF/ACT command period (operation) REF to REF/ACT command period (refresh) ACT to PRE command period PRE to ACT command period ACT to READ/WRITE delay ACT(one) to ACT(another) command period Write recovery time Auto precharge write recovery time + precharge time Mode register set command cycle time Exit self refresh to command Refresh time (4,096 refresh cycles) tRC tRFC tRAS tRP tRCD tRRD tWR tDAL tMRD tXSNR tREF 65 75 45 20 20 15 15 35 15 75 64 120,000 MAX. -C80(PC200) MIN. 70 80 50 20 20 15 15 35 15 80 64 120,000 MAX. ns ns ns ns ns ns ns ns ns ns ms Unit
Preliminary Data Sheet E0187N10
9
Serial PD
Byte No. 0 1 2 3 4 5 6 7 8 9 Function Described Defines the number of bytes written into serial PD memory Total number of bytes of serial PD memory Fundamental memory type Number of rows Number of columns Number of banks Data width Data width (continued) Voltage interface CL = 2.5 Cycle time -C75 -C80 10 CL = 2.5 Access time -C75 -C80 11 12 13 14 15 16 17 18 19 20 21 22 23 DIMM configuration type Refresh rate/type SDRAM width Error checking SDRAM width Minimum clock delay Burst length supported Number of banks on each SDRAM /CAS latency supported /CS latency supported /WE latency supported SDRAM module attributes SDRAM device attributes : General CL = 2 Cycle time -C75 -C80 24 CL = 2 Access time -C75 -C80 25-26 27 tRP(MIN.) -C75 -C80 28 tRRD(MIN.) -C75 -C80 29 tRCD(MIN.) -C75 -C80 30 tRAS(MIN.) -C75 -C80 31 Module bank density 50H 50H 3CH 3CH 50H 50H 2DH 32H 10H 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 1 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 20 ns 20 ns 15 ns 15 ns 20 ns 20 ns 45 ns 50 ns Hex 80H 08H 07H 0CH 09H 02H 40H 00H 04H 75H 80H 75H 80H 00H 80H 10H 00H 01H 0EH 04H 0CH 01H 02H 20H 00H A0H A0H 75H 80H Bit 7 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 Bit 6 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit 5 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 Bit 4 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit 3 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 Bit 2 0 0 1 1 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 Bit 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 Bit 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0
(1/2)
Notes 128 bytes 256 bytes DDR SDRAM 12 rows 9 columns 2 banks 64 bits 0 SSTL_2 7.5 ns 8 ns 0.75 ns 0.8 ns None Normal x8 None 1 clock 2, 4, 8 4 banks 2, 2.5 0 1
Differential Clock
VDD 0.2 V 10 ns 10 ns 0.75 ns 0.8 ns
64M bytes
10
Preliminary Data Sheet E0187N10
(2/2)
Byte No. 32 Function Described Command and address signal input setup time 33 Command and address signal input hold time 34 Data signal input setup time -C75 -C80 -C75 -C80 -C75 -C80 35 Data signal input hold time -C75 -C80 36-61 62 63 SPD revision Checksum for bytes 0 - 62 -C75 -C80 64-71 72 73-90 91 93-94 95-99 Manufacture's JEDEC ID code Manufacturing location Manufacture's P/N Revision Code Manufacturing date Assembly serial number 00H 0 0 0 0 0 0 0 0 00H 94H 1AH 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 1 0 0 0 Hex 90H B0H 90H B0H 50H 60H 50H 60H Bit 7 1 1 1 1 0 0 0 0 Bit 6 0 0 0 0 1 1 1 1 Bit 5 0 1 0 1 0 1 0 1 Bit 4 1 1 1 1 1 0 1 0 Bit 3 0 0 0 0 0 0 0 0 Bit 2 0 0 0 0 0 0 0 0 Bit 1 0 0 0 0 0 0 0 0 Bit 0 0 0 0 0 0 0 0 0 Notes 0.9 ns 1.1 ns 0.9 ns 1.1 ns 0.5 ns 0.6 ns 0.5 ns 0.6 ns
100-127 Mfg specific
Timing Chart
Refer to the PD45D128442, 45D128842, 45D128164 Data sheet (E0030N).
Preliminary Data Sheet E0187N10
11
Package Drawing
67.60 63.60 11.55 18.45 3.80 (DATUM -A-) Unit: mm
4x Full R
Component area (Front)
20.0 4.00
31.75 6.00
2.15
11.40 4.20
A
47.40
B 2.45 1.00 0.10
4.20 1.50 2.45
2
199
1
11.40
47.40
200
2.15 R0.50 0.20
R0.50 0.20
2x 1.80
Component area (Back)
4.00 0.10
(DATUM -A-)
2.00 Min.
Detail A
(DATUM -A-) FULL R
4.00 0.10
Detail B
0.60 1.80 1.00 0.10 0.45 0.03
12
Preliminary Data Sheet E0187N10
0.25 Max
2.55
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0107
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Preliminary Data Sheet E0187N10
13
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107

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